1. Field
The present invention relates to system LSIs, and it particularly relates to a system LSI having plural buses.
2. Description of the Related Art
A system LSI (Large Scale integrated Circuit) internally includes, within one chip, a memory and plural devices having separate functions such as a processor (which will be called CPU hereinafter), an arithmetic circuit, a communication circuit, and an external interface circuit. The memory and the plural devices are mutually connected through a bus, and the bus is used to perform data transfer between the memory and the devices.
As the size of such a system LSI increases, the number of devices to be included therein increases and the size of one chip increases. Thus, it becomes more difficult to connect the internally included memory and the plural devices through one common bus because of physical constraints and constraints with high-speed operations. In other words, connecting many devices contained within a large chip through one common bus is difficult in layout, and the increase in wiring capacitance of the bus may lower the data transfer rate.
Accordingly, system LSIs in recent years have had plural bus systems, and internally included memories and devices have been connected to different buses. Furthermore, the plural buses have been connected through a bus bridge internally including an FIFO, for example, to allow data transfer between the devices and memories connecting to the different buses. Thus, the wires of the buses have been shorter, which has made the layout easier and could keep a high data transfer rate between the devices and memories connecting to the buses.
FIG. 1 is an example of a block diagram of a system LSI in the past. The system LSI has devices including a CPU 3, hardware 4 such as an arithmetic circuit, a peripheral 5 such as an external interface and memories 11 and 12. The system LSI further has two buses 1 and 2. The CPU 3 and a memory controller 13 connect to the bus 1, and the hardware 4, the peripheral 5 and a memory controller 14 connect to the bus 2. Both of the buses 1 and 2 are connected through a bus bridge 10, and through the bus bridge 10, the data transfer between the buses is achieved. The access to the memories 11 and 12 are controlled by the memory controllers 13 and 14.
Because the system LSI illustrated in FIG. 1 has the two buses, when the CPU 3 accesses the memory 11 through the bus 1, the peripheral 5 can access the hardware 4 through the bus 2 simultaneously. Furthermore, the CPU 3 may access the memory 12 through the bus 1, bus bridge 10 and bus 2. In this way, the memories and devices connecting to different buses may be accessed each other.
Japanese Laid-open Patent Publication No. 08-185359 discloses a bus bridge that matches a cache memory and a main storage memory in order for a processor to perform proper data processing in a multi-level cache in NUMA, which is a protocol for a multiprocessor system.
Japanese Laid-open Patent Publication No. 09-34741 discloses a memory copy system including a counter exhibiting a memory address in an information processing system which is redundantly including plural subsystems each having a memory in order to perform memory copy between/among the subsystems. With reference to the counter, a program, for example, may be read from the corresponding address as required and be copied to the memory in a different subsystem.
Japanese Examined Patent Application Publication No. 07-9625 discloses a configuration of a computer having a fault-tolerant capability by using plural CPUs, plural memories and plural buses.